半导体静电放电保护装置

Abstract

本发明公开一种半导体静电放电保护装置,包括:第一电性晶体管、第二电性阱区、第二电性保护环以及半导体间隔区。第一电性晶体管,形成于第二电性阱区之中。第二电性保护环,围绕第一电性晶体管。半导体间隔区,位于第一电性晶体管和第二电性保护环之间,并围绕第一电性晶体管,且半导体间隔区为无掺杂区、第一电性掺杂区或掺杂浓度小于第二电性阱区的第二电性掺杂区。
The invention discloses a semiconductor electrostatic discharge protection device, which comprises a first electric transistor, a second electric trap region, a second electric protection ring and a semiconductor separation region, wherein the first electric transistor is formed in the second electric trap region, the second electric protection ring surrounds the first electric transistor, the semiconductor separation region is positioned between the first electric transistor and the second electric protection ring, and surrounds the first electric transistor, and in addition, the semiconductor separation region is a non-doping region, a first electric doping region or a second electric doping region with the doping concentration being smaller than that of the second electric trap region.

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    CN-105304625-AFebruary 03, 2016北京时代民芯科技有限公司, 北京微电子技术研究所SRAM type FPGA double-array-hole electrostatic discharge protection layout structure for aerospace